This invention relates to a composite semiconductor device in which a bipolar transistor and a MIS transistor are formed on a semiconductor substrate and to a method of manufacturing the semiconductor.
There has been many semiconductor devices with Bi-CMOS structure proposed in which a bipolar transistor and a complementary MOS transistor (CMOS transistor) are integrally formed.
As a method of manufacturing a general semiconductor with Bi-CMOS structure, a method disclosed in Japanese Patent Application Laying Open Gazette No. 64-59952 is explained, with reference to FIGS. 23-25.
As shown in FIG. 23, an N.sup.+ buried layer 3 and a P.sup.+ buried layer 4 are formed on a P-type silicon substrate 1 and an N.sup.- type epitaxial layer 6 are formed thereon. After a P-well 6a is provided on the N.sup.- type epitaxial layer 6, a field insulator film 17f is formed on a part of the surface of the substrate according to a selective oxidization process so as to define a region Rbip where a bipolar transistor is to be formed, a region Rnmos where an NMOS transistor is to be formed, and a region Rpmos where a PMOS transistor is to be formed. A silicon oxide film 17 as a dielectric film is formed and a P.sup.- type active base region 11 of an NPN bipolar transistor is formed.
Then, as shown in FIG. 24, the silicon surface is exposed by etching the silicon oxide film 17 on the P.sup.- type active base region 11, using a resist as a mask or the like so as to make an emitter contact hole 19a. A polysilicon film 21 of 300 nm thickness is laid on the substrate according to a low pressure CVD method.
Next, as shown in FIG. 25, the polysilicon film 21 is etched using the resist as a mask to form an emitter polysilicon electrode 21a in the region Rbip where the bipolar transistor is to be formed, and to concurrently form gate polysilicon electrodes 21f in the region Rnmos where the NMOS transistor is to be formed and the region Rpmos where the PMOS transistor is to be formed. Then, implant and diffusion of arsenic ions are selectively conducted over the substrate to form an N.sup.+ emitter layer 23 of the NPN bipolar transistor and a source 14a and a drain 14b of an NMOSFET. At this time, the arsenic is also doped to a gate polysilicon electrode 21f of the NMOSFET. Further, implant and diffusion of boron ions are conducted to form a grafting base region 11a of the NPN bipolar transistor and a source 15a and a drain 15b of the PMOSFET. At this time, the boron is also doped to the gate polysilicon electrode 21f of the PMOSFET.
Thus manufactured is the semiconductor device with Bi-MOS structure.
The above semiconductor device and the method thereof, however, have following problems.
(1) The silicon oxide film 17 is contaminated by resist coating, etching, and the like, since the step of forming the contact holes such as the emitter diffusion hole 19a of the bipolar transistor is carried out after the step of forming the silicon oxide film 17 and before the step of laying the polysilicon film 21.
(2) It is required to conduct dip-etching for removing a natural oxide film on the N.sup.+ emitter layer 23 after the step of forming the emitter contact hole 19a and before the step of laying the polysilicon film 21. However, in conventional semiconductor device and method thereof, in case with the silicon oxide film 17 of about 10 nm thickness, such dip-etching reduces the thickness of the silicon oxide film 17 further, so that variation of the characteristic and deficiency due to pin holes are caused. This involves a problem in a MOSFET. In the bipolar transistor, since the silicon oxide film 17 is used as an insulator film between a subsurface silicon substrate and the polysilicon film 21 which serves as an emitter diffusion mask and an emitter electrode, deficiency in durability to high voltage between the emitter and the base and increase in leakage current are caused.
On the other hand, Japanese Patent Application Laying Open Gazette No. 3-148862 discloses a method in order to enhance the performance of a bipolar transistor, which is required accompanied by miniaturization of elements. The method is that: a silicon oxide film is formed as a gate insulator film on an entire substrate before the contact hole of the bipolar transistor is made; after a polysilicon film to be a part of a gate electrode is laid on the silicon oxide film and the polysilicon film on an active region of the bipolar transistor is removed by etching, a thick silicon oxide film is further laid thereon; the contact hole of the bipolar transistor is made at the same time as the silicon oxide film of the MOS transistor is removed; and a polysilicon film to be a part of the electrode of the bipolar transistor and the gate electrode of the MOS transistor is laid thereon. In this method, since the silicon oxide film of the gate electrode of the MOS transistor is covered with the polysilicon film at the formation of contact hole of the bipolar transistor, the contamination to the silicon oxide film can be lessened. However, the step of removing the polysilicon at the active region of the bipolar transistor is required beside the step of forming the contact hole of the bipolar transistor, which means increase in manufacturing steps. Therefore, the cost increases though the contamination to the gate insulator film is prevented.
The present invention has its object of providing a semiconductor device and a method of manufacturing a semiconductor device where the MIS transistor and the bipolar transistor formed on the semiconductor substrate which has high reliability without increase in manufacturing steps and cost by providing a protection means to the gate insulator film on the semiconductor substrate at the MIS transistor at the formation of contact hole on the active region of the bipolar transistor.